Memory and embedded Architecture Research Group

Welcome to the homepage of MARG, our research group led by Prof. Preeti Ranjan Panda in the CSE Dept. and School of IT at Indian Institute of Technology Delhi.

Our research group investigates several research problems that arise at the intersection of Embedded Systems and the adjacent areas of Computer Architecture, Compilers, and Systems-on-Chip design. How do we save energy while not sacrificing performance in computing systems? How do we restructure data and computation to take advantage of performance and power optimisation opportunities? What are the system-level implications of emerging memory technologies?


Our Research spans the areas of :

  • Energy-efficient Embedded Systems
  • Shared Cache Management
  • Hardware Architectures for AI/Machine Learning
  • Application Specific Hardware and Hardware Accelerators
  • Emerging Memory Technologies: 3D and Non-Volatile Memory
  • Electronic Design Automation and Design Methodology
  • High-Level and System Level Synthesis
  • News
    • Year 2020
    • [Oct 2020] Research Paper Leakage-Aware Dynamic Thermal Management of 3D Memories, by L. Siddhu, R. Kedia, P. R. Panda, published in ACM Transactions on Design Automation of Electronic Systems (TODAES), 26(2):1-31, October 2020
    • [Aug 2020] PhD Student Ayushi Agarwal wins the prestigious Prime Minister's Research Fellowship (PMRF)
    • [Feb 2020] Survey paper A survey of cache simulators by H. Brais et al. published in ACM Computing Surveys, (CSUR), 53(1):19:1-19:32, Feb 2020
    • [Jan 2020] P. R. Panda is appointed Editor-in-Chief of IEEE Embedded Systems Letters (ESL) journal
    • Year 2019
    • [Nov 2019] Neetu Jindal is conferred the PhD degree at IITD's 50th Convocation ceremony. She was part of the research collaboration with Freescale/NXP and SRC. Now at Intel.
    • [Oct 2019]Research paper PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor by L. Siddhu and P. R. Panda presented at CODES+ISSS'19 , New York
    • [Oct 2019] Research paper Alleria: An Advanced Memory Access Profiling Framework by H. Brais and P. R. Panda presented at CODES+ISSS'19 , New York
    • [Oct 2019] Research paper REAL: REquest Arbitration in Last Level Caches by S. Tiwari, S. Tuli, I. Ahmad, A. Agarwal, P. R. Panda, and S. Subramoney, published in ACM TECS 18(6): 115:1-115:24 (2019)
    • [Aug 2019] New research project Algorithms and Architectures for Machine Learning and Computing on the Edge sponsored by Cadence Design Systems initiated.
    • [Aug 2019] Book chapter Manycore processor architectures by P. Chakraborty, B. N. Swamy, and P. R. Panda published in Many-Core Computing: Hardware and Software, eds. B. M. Al-Hashimi and G. V. Merrett, IET
    • [Jul 2019] P. R. Panda delivered the keynote address at VDAT'19, Indore
    • [Mar 2019] Research paper "FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories" by Lokesh Siddhu and P. R. Panda presented at DATE'19, Florence.
    • [Feb 2019] Research paper DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring by Neetu Jindal, Sandeep Chandran, et al. presented at DAC 2019
    • [Feb 2019] Research paper Enhancing Network-on-Chip Performance by Reusing Trace Buffers by Neetu Jindal,Shubhani Gupta, Divya Praneetha et al. published in IEEE Transactions on CAD.
    • [Jan 2019] Rahul Jain wins the Best PhD Thesis Award at the 32nd Intl. Conf. on VLSI Design and 18th Intl. Conf. on Embedded Systems for his thesis titled Machine Learned Machines: Reinforcement Learning Exploration for Architecture Co-optimization. The research was supported by Intel and DST/SERB's PM Fellowship program.
    • [Jan 2019] Ayushi Agrawal (with team-mates Anupam Sobti and Saurabh Tewari) wins the first prize in the Cadence Tensilica Hackathon at VLSID 2019
    • [Jan 2019] P. R. Panda is the general co-chair of the 32nd Intl. Conf. on VLSI Design and 18th Intl. Conf. on Embedded Systems
    • Year 2018
    • [Nov 2018] Sandeep Chandran is awarded the PhD degree at the 49th Convocation. Wins the FITT Award (incl. cash prize of Rs. 60,000) for the Best Industry Relevant PhD Project in IIT Delhi. Freescale/NXP Semiconductor and Semiconductor Research Consortium were collaborators.
    • [Nov 2018] Research paper "FastCool: Leakage Aware Dynamic Thermal Management of 3D Memories" by Lokesh Siddhu and P. R. Panda presentation at DATE'19 , Florence.
    • [Jul 2018] Isaar Ahmed, Aritra Bagchi, and Ayushi Agarwal join our research group. Welcome!
    • [Sep 2018] P. R. Panda is Head, Amar Nath and Shashi Khosla School of Information Technology, IIT Delhi
    • [Apr 2018] Research paper "Reusing Trace Buffers as Victim Caches" by Neetu Jindal et al. published in IEEE Transactions on VLSI Systems (TVLSI) 26(9): 1699-1712 (2018).
    • [Apr 2018] Lecture video series for the online course "Synthesis of Digital Systems" available on Youtube. Link to videos
    • [Jan 2018] Book chapter: P. R. Panda, "Memory Architectures" published in S. Ha and J. Teich, "Handbook of Hardware/Software Codesign", Springer, 2017.
    • [Jan 2018] P. R. Panda is an Associate Editor of IEEE Transactions on CAD.
    • Year 2017
    • [Oct 2017] Rahul Jain defends his PhD thesis
    • [Aug 2017] Research paper "Cooperative Multi-Agent Reinforcement Learning based Co-optimization of Cores, Caches, and On-chip Network" by R. Jain, P. R. Panda, and S. Subramoney published in ACM Transactions on Architecture and Code Optimization (TACO), 14(4):32:1-32:25, 2017.
    • [Jun 2017] New Research Project on Smartphone Energy Efficiency sponsored by Samsung initiated.
    • [May 2017] New Research Project on Memory Hierarchy in Multiprocessor Systems-on-Chip sponsored by Semiconductor Research Corporation (SRC) initiated.
    • [Mar 2017] Research paper "A Coordinated Multi-Agent Reinforcement Learning Approach to Multi-Level Cache Co-partitioning" by Rahul Jain, P. R. Panda, and S. Subramoney, presented at DATE'17, Lausanne.
    • [Mar 2017] Research paper "Reusing Trace Buffers to Enhance Cache Performance" by Neetu Jindal et al., presented at DATE'17, Lausanne.
    • [Feb 2017] P. R. Panda delivered inaugural talk "Embedded Systems-on-Chip: Research at the Forefront of VLSI Systems" and seminars on Hardware Synthesis at Faculty Development Programme in MNIT Jaipur.