Collaborators: Prof. Dr. Hussam Amrouch, Technical University of Munich
There is a rise in on-chip power density due to on-chip transistor density and the breakdown of Dennard’s scaling. Dennard’s scaling states that as transistors get smaller with each generation, their power densities stay constant due to voltage scaling with length. Voltage scaling came to a halt a decade ago as voltages can not be scaled down in proportion to the scaling down of transistors. This led to the inability to increase clock frequencies in single-core systems. The advent of multi-core processors came to the rescue to improve performance. With the systems having a limited power budget, several on-chip components must be power gated to stay within the power budget, which may impact performance. The inability to scale down operating voltages with transistor scaling due to the sub-threshold slope (SS) of 60mV/decade of CMOS transistors has impacted frequency and power.
Ferroelectric-based Negative Capacitance FinFETs (NCFET) gained significant momentum due to the breakthrough of the SS limit of 60mV/decade and revived Dennard’s Scaling. This could lead to the revival of voltage and frequency scaling. Negative Capacitance FinFETs (NCFET) are the transistors with a ferroelectric (FE) layer in their gate stack, as shown in Figure 1. The FE layer manifests itself as negative capacitance (shown in Figure 1), thus providing gate voltage amplification. The higher voltage observed by the internal metal gate results in a stronger formation of the conductive channel below the gate, yielding higher driving strength (ON-current). Additionally, NCFET exhibits a lower leakage current (OFF-current) than FinFET at any given voltage due to the negative-DIBL characteristics of NCFET.
The energy optimization techniques in FinFET(/CMOS)-based systems consider reducing power consumption without penalising performance. Operating voltage must be reduced whenever the workload of the system reduces to optimize energy. Power reduction techniques in FinFET-based caches also include power-gating the cache blocks to reduce leakage power. As leakage power is lower for NCFET than that of FinFET, we may not reduce voltage to save energy for NCFET-based systems. Existing FinFET-based energy-saving techniques do not result in optimal energy savings for NCFET-based systems. We propose to address the following problems in this thesis:
- NCFET-based cache energy optimization
- Energy optimization for NCFET-based multi-core system
Publications:
- D. P. Ravipati, R. Kedia, V. M. Van Santen, J. Henkel, P. R. Panda and H. Amrouch, FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 3, pp. 339-352, March 2022, doi: 10.1109/TVLSI.2021.3123112.
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