Post Silicon Validation in System-on-Chip
Collaborators: Freescale and Semiconductor Research Corporation (SRC)
As the computer industry moves towards the era of multi-core and many-core SoCs with a large number of processor cores and accelerators, there is an urgent need for revamping the post-silicon validation methodologies, and re-architecting the hardware debug mechanisms.
Robust validation methodologies play a vital role in the chip design flow, as the industry struggles to contain costs under increasing design complexity. In this research we attempt a scalable debug methodology that is sensitive to the requirements of handling large amounts of debug data with area constraints, and explore the possibility of reusing debug hardware to improve performance.
